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IBPS > Computer Architecture

Explore popular questions from Computer Architecture for IBPS. This collection covers Computer Architecture previous year IBPS questions hand picked by experienced teachers.

Q 1.

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Where does a computer add and compare data?

A

Hard disk

B

Floppy disk

CPU chip

D

Memory chip

E

None of these

Q 2.

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Which of the following registers is used to keep track of address of the memory location where the next instruction is located?

A

Memory Address Register

B

Memory Data Register

C

Instruction Register

Program Register

E

None of these

Q 3.

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Pipelining strategy is called implement

A

instruction execution

instruction prefetch

C

instruction decoding

D

instruction manipulation

E

None of these

Explanation

Pipelining is a technique to build fast processors. It allows the execution of multiple instruction by overlapping them. In an assembly unit every stage has one and only one activity to do. It keeps repeating them again and again. In the same way in a instruction pipeline at every clock cycle one particular step of multiple instruction will be performed Every instruction has multiple stages. Say at the first clock cycle first step of instruction1 is performed At the second clock cycle the second step of instruction1 and 1st step of instruction2 would be performed and so on. So pipelining is called instruction prefetch. So the option is (b)

Q 4.

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When the RET instruction at the end of subroutine is executed,

A

the information where the stack is initialized is transferred to the stack pointer

B

the memory address of the RET instruction is transferred to the program counter

two data bytes stored in the top two locations of the stack are transferred to the program counter

D

two data bytes stored in the top two locations of the stack are transferred to the stack pointer

E

None of these

Q 5.

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What is meant by a dedicated computer?

A

which is used by one person only

which is assigned to one and only one task

C

which does one kind of software

D

which is meant for application software only

E

None of these

Q 6.

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The most common addressing techniques employed by a CPU is

A

immediate

B

direct

C

indirect

D

register

all of these

Q 7.

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Interrupts which are initiated by an instruction are

A

internal

B

external

C

hardware

software

E

None of these

Explanation

There are three types of interrupts. They are
1. External interrupts
2. Internal interrupts
3. Software interrupt
External interrupts come from I/O devices. Internal interrupts are from illegal or wrong use of an instruction or data. A software interrupt is initiated by executing an instruction.

Q 8.

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MIMD stands for _______.

Multiple instruction multiple data

B

Multiple instruction memory data

C

Memory instruction multiple data

D

Multiple information memory data

E

None of these

Q 9.

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The average time required to reach a storage location in memory and obtain its contents is called_________.

A

Latency time

Access time

C

Turnaround time

D

Response time

E

None of these

Q 10.

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Memory unit accessed by content is called______.

A

Read only memory

B

Programmable Memory

C

Virtual Memory

Associative Memory

E

None of these

Q 11.

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n bits in operation code imply that there are _________possible distinct operators.

A

{tex}\mathrm {3n}{/tex}

{tex}\mathrm {2n}{/tex}

C

{tex}\mathrm {n/{2}}{/tex}

D

{tex}\mathrm n^{2}{/tex}

E

None of these

Q 12.

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The multiplicand register & multiplier register of a hardware circuit implementing booth's algorithm have (11101) & (1100). The result shall be ___________.

(812)10

B

(-12)10

C

(12)10

D

(-812)10

E

None of these

Q 13.

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PSW is saved in stack when there is a ______.

interrupt recognized

B

execution of RST instruction

C

Execution of CALL instruction

D

All of these

E

None of these

Q 14.

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In computers, subtraction is carried out generally by______.

A

1's complement method

2's complement method

C

signed magnitude method

D

BCD subtraction method

Q 15.

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Cache memory works on the principle of______.

A

Locality of data

B

Locality of memory

Locality of reference

D

Locality of reference & memory

E

None of these

Explanation

A cache is a simple example of exploiting temporal locality, because it is a specially designed faster but smaller memory area, generally used to keep recently referenced data and data near recently referenced data, which can lead to potential performance increases.

Q 16.

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When CPU is executing a Program that is part of the Operating System, it is said to be in ___.

A

Interrupt mode

System mode

C

Half mode

D

Simplex mode

E

None of these

Q 17.

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Register renaming is done in pipelined processors

A

as an alternative to register allocation at compile time

B

for efficient access to function parameters and local variables

to handle certain kinds of hazards

D

as part of address translation

Explanation

Register remaining is done is pipelined processors to handle certain kinds of hazards.

Q 18.

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The amount of ROM needed to implement a 4 bit multiplier is

A

64 bit

B

128 bit

C

1 kbit

2 kbit

E

None of these

Explanation

The normal size of ROM is {tex}\mathrm {n × 2^n}{/tex}.
Now, we are multiplying two n-bit numbers.
So, the resultant has 2n bit. Hence, the size of the ROM is {tex}\mathrm {2n}{/tex} x {tex} \mathrm {2^{2n}}{/tex}. In the question, {tex} \mathrm n {/tex}=4 Hence {tex}\Rightarrow{/tex} 2x4x2{tex}^{2\times 4}{/tex} {tex} \Rightarrow {/tex} 8x2{tex}^8{/tex} {tex}\Rightarrow{/tex} 2{tex}^3{/tex} x 2{tex}^8{/tex} {tex}\Rightarrow{/tex} 2 x 2{tex}^8{/tex} {tex}\Rightarrow{/tex}2k bit

Q 19.

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A computer handles several interrupt sources of which of the following are relevant?
Interrupt from CPU temperature sensor
Interrupt from Mouse
Interrupt from Keyboard
Interrupt from Hard disk

A

Interrupt from Hard disk

B

Interrupt from Mouse

C

Interrupt from Keyboard

Interrupt from CPU temperature sensor

E

None of these

Q 20.

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How many 32 k x 1 RAM chips are needed to provide a memory capacity of 256 kbyte?

A

8

B

32

64

D

128

E

None of these

Explanation

As given, basic RAM is 32 k × 1 and we have to design a RAM of 256 k × 8.
Therefore, number of chips required =
256 k × 8/(32 k × 1) =
245 × 1024 × 8/32 × 1024 × 1)
(Multiplying and dividing by 1024)
= 64 = 8 × 8 Means,
64 = 8 parallel lines × 8 serial RAM chips.

Q 21.

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A CPU generally handles an interrupt by executing an interrupt service routine

A

as soon as an interrupt as raised

B

by checking the interrupt register at the end of fetch cycle

by checking the interrupt register after finishing the execution of the current instruction

D

by checking the interrupt register at fixed time intervals.

E

None of these

Explanation

The interrupt register is checked after finishing the execution of the current instruction. At this time, a CPU generally handles an interrupt by the execution of an interrupt service routine.

Q 22.

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For a magnetic disk with concentric circular tracks, the seek latency is not linearly proportional to the seek distance due to

A

non-uniform distribution of requests

B

arm starting and stopping inertia

higher capacity of tracks on the periphery of the platter

D

use of unfair arm scheduling policies

E

None of these

Explanation

The seek latency is not linearly proportional to seek distance due to the higher capacity of tracks on the periphery of the latter. The higher capacity of the tracks is responsible for the presence of this certain amount of time is required for this cells to reach the read-write head so that data transfer can take place.

Q 23.

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Consider a 4-way set associate cache consisting of 128 lines with a line size of 64 words. The CPU generates a 20-bit address of word in main memory. The number of bits in the TAG, LINE and WORD fields are respectively.

A

9, 6, 5

7, 7, 6

C

7, 5, 8

D

9, 5, 6

E

None of these

Explanation

7 bits are required if there are 128 lines. The reason behind is that 128 is 2{tex}^7{/tex}.
Now, each line is of 64 words or 2{tex}^6{/tex} words.
Hence, number of bits required is 6 bit as 64 or 2{tex}^6{/tex}.
As per the given, a 20 bit address is generated for a word in main memory, so bits required for tag = 20 – (7 + 6) = 20 – 13 = 7 bit.

Q 24.

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Consider a disk pack with 16 surfaces, 128 tracks per surface and 256 sectors per track. 512 byte of data are stored in a bit serial manner in a second. The capacity of the disk pack and the number of bits required to specify a particular section in the disk are respectively

256 Mbyte, 19 bit

B

256 Mbyte, 28 bit

C

512 Mbyte, 20 bit

D

64 Gbyte, 28 bit

E

None of these

Explanation

Q 25.

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A CPU has 24-bit instructions. A program starts at address 300 (in decimal). Which one of the following is a legal program counter (all values in decimal)?

400

B

500

C

600

D

700

E

None of these

Explanation

Each address is multiple of 3 as the starting address is 300 and is each instruction consists of 24 bit, i.e., 3 byte. Thus, in the given options the valid counter will be the one which is the multiple of 3. Out of the options we can see that only 600 satisfies the condition. Therefore, it is 600.